An integrated circuit is formed, in part, by defining patterns in various layers grown or deposited on a semiconductor wafer surface. The patterned layers may, for example, define the doped regions in the wafer or the metal interconnections between the regions.
Typically, in forming the various layers on a semiconductor wafer to create an integrated circuit, the wafer is covered with a film of photoresist, and this photoresist layer is selectively exposed to radiation, such as ultraviolet radiation. If the photoresist is a negative photoresist, the exposed portions of the photoresist become hard and are not dissolved away in a subsequent developing process, while the unexposed portions of the negative photoresist are easily dissolved away during the developing process. If the photoresist is a positive photoresist, the exposed portions of the photoresist are easily dissolved away in the developing process, and the unexposed portions of the photoresist are insoluble in the developing solution.
The photoresist is exposed by interposing a mask between the radiation source and the wafer. The mask has an optically opaque pattern on it which corresponds to the pattern to be defined in the photoresist.
After exposure of the photoresist, the wafer is typically dipped in a developing solution for dissolving away the soluble portions of the photoresist to selectively expose the underlying layer. A next step in the wafer fabrication process may include doping, implantation, etching, oxidation, or any other process.
FIG. 1 illustrates a conventional prior art mask 10 of the type which contains the entire pattern to be formed in a photoresist layer on a wafer. A typical mask 10 contains a generally circular chrome pattern 12, which is larger than the wafer, where this chrome pattern 12 is formed on a square quartz substrate 14. The chrome portions of the pattern 12 are opaque to UV light. The chrome pattern 12 contains the entire pattern to be defined on the wafer's surface.
There are various ways to form chrome pattern 12 on quartz (or other transparent) substrate 14. One method is to form a solid chrome layer on quartz substrate 14, dispense a layer of photoresist over the chrome layer, then selectively expose the photoresist to light to define the mask pattern. The photoresist may be selectively exposed using a 5X or 10X reticle having one or more enlarged die patterns formed on it. The reticle is then stepped and repeated across the photoresist surface to define the mask pattern. The photoresist layer is then developed, and the exposed underlying chrome layer is then etched to form the pattern 12 in FIG. 1.
Another way to form the chrome pattern 12 is to form a layer of chrome on the quartz substrate 14 and use a scanning electron beam to selectively etch away portions of the chrome layer. The electron beam is controlled by a computer which is programmed with the desired mask pattern.
The mask 10 of FIG. 1 may be used in a projection-type exposure system or a contact-type exposure system where the mask is placed in direct contact with the wafer surface.
The typical cost for a single mask 10 is approximately $1,000, and there may be as many as twelve or more masks used for forming an integrated circuit product. When developing and testing a product, frequently masks must be modified so that multiple versions of the same mask may be required before achieving a final design. If only a relatively few numbers of chips are required to meet the consumers' needs, the costs of these masks become a significant portion of the product's manufacturing cost.
One way which has been used in the past to limit the costs of masks for a product is illustrated with respect to FIG. 2. In FIG. 2, a single mask 20 is fabricated which contains two or more patterns for concurrently forming two or more patterns on a wafer surface in a single exposing step in order to form two or more products on the same wafer. The mask 20 of FIG. 2 illustrates three different chrome patterns 22, 23, 24 formed on the same mask 20 for forming three different products on the same wafer. After the wafer is completely processed, the wafer is tested and diced, and the dice for the three products are separated out and packaged.
An advantage of the mask of FIG. 2 is that only one-third of the masks are required to form the three products, which would save approximately $24,000, assuming each product required twelve exposing steps.
The main problem with mask 20 of FIG. 2 is that rarely are three product mask designs finalized at the same time. For example, the final design for product 3, formed using pattern 24 in FIG. 2, may be late to finish, which would delay the introduction of products 1 and 2, formed using mask patterns 22 and 23. This would be a serious problem in today's fast-paced electronics industry. Accordingly, the mask of FIG. 2 and similar type mask designs are not useful when products must be introduced in a timely fashion.
Also, using mask 20, significant delays will often occur since, if one layer needs to be modified on one product, the economical designer will wait until it is assured that the other products will not need changes on the same layer.
Further, by using mask 20 of FIG. 2, if there is a need to change the mask pattern for one of the products, another mask must be fabricated, and this could undesirably cause slight variations in the other mask patterns due to variances in the mask formation process.
Still further, mask 20 of FIG. 2 is not suitable for production runs since the demands for one of the products 1, 2, and 3 may change, while the same relative quantities of the products 1, 2, and 3 must keep being produced using the fixed mask pattern of FIG. 2.
Additionally, if products 1, 2 and 3 do not use the same technologies (e.g., CMOS, bipolar, etc.), this may greatly complicate the wafer fabrication process. Similarly, if the various products 1, 2 and 3 require different line widths or contact hole sizes, this may additionally complicate the wafer fabrication process.
Thus, the general mask type of FIG. 2 has only limited usefulness.
The most common and inexpensive types of exposure systems use the wafer-size masks of FIGS. 1 or 2, where the full mask image completely covers the wafer without any stepping of the mask image across the wafer. The exposure systems which utilize such masks may automatically align the masks with respect to a reference target on the wafer surface, or the alignment may be made manually by an operator using a microscope. Thus, for typical integrated circuits, such conventional alignment and exposure systems, whether projection or contact mask systems, are desirable to produce relatively inexpensive chips. For smaller wafer fabrication facilities, the large expense of buying state of the art step-and-repeat exposure systems, which step a reticle across the wafer surface to expose the photoresist layer, is not justified for the volume of chips produced.
Thus, what is needed is a new type of mask configuration and photoresist exposure method which limits the costs of masks used for forming integrated circuits and which can make use of the relatively inexpensive, conventional projection or contact exposure systems.